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nexflash technologies, inc. 1 preliminary nxsf006e-0801 08/22/01 ? nx26f080a nx26f160 8m-bit and 16m-bit serial flash memory with 2-pin nxs interface features ? tailored for portable and mobile media-storage ? ideal for portable/mobile applications that transfer and store data, audio, or images ? removable serial flash module package option nexflash ? non-volatile memory technology ? patented single-transistor eeprom cell ? high-density, cost-effective, low-voltage/power ? 10k/100k endurance, ten years data retention flash memory for battery-operation ? single 5v or 3v supply for read, erase/write ? icc 15 ma active with 1 a standby power ? 5 ms erase/write times for efficient battery use 8m-bits or 16m-bits of nexflash serial memory ? 2,048 or 4,096 sectors of 536 bytes each ? simple commands: reset, read, write, ready/busy ? no pre-erase required, auto-erases before write two-pin nxs serial interface ? saves microcontroller-pins, simplifies pcb layout, low switching noise compared to parallel flash ? supports clock operation as fast as 16 mhz ? multi-device cascading, up to 16 devices development tools and accessories ? nx-sfk-nxs serial flash development kit description the nexflash ? nx26f080a and nx26f160 serial flash memories are tailored for portable/mobile media-storage applications that transfer and store data, audio and images. manufactured using nexflash ? s patented single transistor eeprom memory cell, the nx26f080a and nx26f160 provide a high-density, low-voltage, low-power, and cost effective solution for battery-operated nonvolatile data stor- age requirements. the nx26f080a and nx26f160 can operate with a single 5v or 3v supply for read, write, and erase. power consumption is very low due to a standby current and fast erase/write performance (as fast as 5 ms per sector) that minimizes power-on time, resulting in a highly efficient energy-per-transfer ratio. the nx26f080a preliminary august 1999 and nx26f160 offer 8m-bits and 16m-bits of flash memory organized in sectors of 536 bytes each. each sector is individually addressable through basic commands or con- trol functions such as reset, read, erase/write, and ready/busy. the nxs ( nexflash serial) 2-wire serial interface is ideal for use with microcontrollers since it only requires two pins. this leaves pins normally used for parallel flash free for other uses. the nxs interface supports clock rates as fast as 16 mhz and allows for multi-device cascading of up to 16 devices. it also simplifies pc-board layout and generates less transient noise than parallel devices. devel- opment is supported with the nexflash serial flash development kit. this document contains preliminary information. nexflash reserves the right to make changes to its product at any time without notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? ? ? ? ? copyright 1998, nexflash technologies, inc.
nx26f080a nx26f160 2 nexflash technologies, inc. preliminary nxsf006e-0801 08/22/01 ? pin descriptions package types the nx26f080a and nx26f160 is available in a 24/28-pin tsop (type ii) package (figure 1 and table 1) or a removable serial flash module (see nx25mxxx/nx26mxxx serial flash module data sheet for further information). power supply pins (vcc and gnd) the nx26f080a and nx26f160 support single power supply read, erase, and write operations available in 5v and 3v vcc versions. active power requirements are as low as 15 ma for 3v versions with standby current in the 1 a range. nxs serial interface pins (sck and sio) the 2-wire nxs (nexflash serial) interface includes a clock input pin (sck) and a single bidirectional i/o pin for data (sio). all data to or from the sio pin is clocked relative to the rising edge of sck. the 2-wire nxs serial interface makes the nx26f080a and nx26f160 an ideal solution for removable non-volatile storage. a simple edge connector or cable/connector with four contacts (sck, sio, vcc, and gnd) can support communications with space efficiency and reliability. the nxs interface can operate at clock rates up to 16 mhz for 5v versions. device address pins (a0, a1, a2, a3) there is no active chip select on the nx26f080a and nx26f160. instead, four static device address pins (a0, a1, a2, and a3) are provided for decoding from one to 16 possible devices (figure 2). this allows up to 16mb (using an nx26f080a device) or 32mb (using an nx26f160 device) to be addressed via a single 2-wire nxs interface. the static address pins (a0-a3) must be tied high or low to match the device address field (da3-da0) in the sector read and erase/write instruction sequences. no connect pins (n/c) the nx26f080a and nx26f160 uses only a few signal pins. as a result, the tsop package has numerous no connects (nc) that have no electrical contact to the die. table 1. pin descriptions a0, a1, a2, a3 device address sck serial clock sio serial data i/o vcc power supply gnd ground nc no connect a0 sck sio vcc nc nc nc nc a3 a2 a1 gnd n/c nc nc nc nc nc nc nc nc nc nc nc 1 2 3 4 5 6 9 10 11 12 13 14 28 27 26 25 24 23 20 19 18 17 16 15 figure 1. nx26f080a and nx26f160 pin assignments
1 2 3 4 5 6 7 8 9 10 11 12 nexflash technologies, inc. 3 preliminary nxsf006e-0801 08/22/01 ? nx26f080a nx26f160 .... .... nx26f080a or nx26f160 u0 nx26f080a or nx26f160 u8 nx26f080a or nx26f160 u9 nx26f080a or nx26f160 u10 nx26f080a or nx26f160 u11 nx26f080a or nx26f160 u1 nx26f080a or nx26f160 u2 nx26f080a or nx26f160 u3 sck sio microcontroller / microprocessor dsp or asic 0a0 0a1 0a2 1a3 1a0 0a1 0a2 1a3 0a0 1a1 0a2 1a3 1a0 1a1 0a2 1a3 1a0 1a1 0a2 0a3 0a0 1a1 0a2 0a3 1a0 0a1 0a2 0a3 0a0 0a1 0a2 0a3 figure 2. nx26f080a or nx26f160 used in a multi-device configuration with up to 16-devices on the 2-wire nsx functional overview the nexflash nx26f080a and nx26f160 provide up to 8m-bits or 16m-bits of non-volatile memory organized as 2,048 or 4,096 small sectors of 536 bytes (4,288 bits) each (figure 3). each sector is individually addressable using basic instruction sequences and control functions commu- nicated through the devices 2-wire nxs interface. read and erase/write instruction sequences the nx26f080a and nx26f160 have two basic instruction sequences: read and erase/write. unlike some other flash technologies, the erase and w rite operations of the nx26f080a and nx26f160 are performed together in one single operation (as fast as 5 ms per sector). thus, pre- erase of the memory is not necessary. both read and erase/write instructions are made up of a series of serial bit fields that include command, sector address, device address, and sector data. the read instruction sequence also allows the device to be polled for ready/busy status. sector 0 (0000h) 4288 bits (536 bytes) per sector sector 1 (0001h) sector 2 (0002h) sectors 3-2045/4093 (0003-07fd/0ffdh) sector 2046/4094 (07fe/0ffeh) sector 2047/4095 (07ff/0fffh) figure 3. nexflash?s nx26f080a and nx26f160 array
nx26f080a nx26f160 4 nexflash technologies, inc. preliminary nxsf006e-0801 08/22/01 ? the instruction sequence format, flow charts, and clocking diagrams for read and erase/write operations are shown in figures 5 and 6, figures 7 and 8, and figures 9 and 10, respectively. all data within an instruction sequence is clocked on the rising edge. all instruction sequence fields are ordered by most significant bit first (msb). data is erased and written to the nx26f160 and nx26f080a memory array a full sector (536 bytes) at a time. if all 536 bytes of a given sector are not fully clocked into the device, the remaining byte locations will be overwritten with indeterminate values. to ensure the highest level of data integrity write operations should be verified and rewritten, if needed, (see high data integrity applications). reset and idle upon power-up and between read and erase/write instruc- tion sequences, the device ? s internal control logic will be reset. this is accomplished by asserting the sck pin low (to v il ) for greater than t reset . once reset, the device enters standby operation and will not wake-up until the next rising edge of sck. after an initial rising sck occurs, the device becomes ready for a new instruction sequence. full active power consumption starts after the correct device address is decoded during a read or write instruction sequence. to idle an instruction sequence between clocks, sck must be kept high (at v ih ) for as long as needed. note that power will be in the active state when sck is held high. device initialization after power-up it is recommended that the device information sector be read to electronically identify the device. the device information format contains a device id that identifies the manufacturer, part number (memory size), and operating range. it also contains a list of any restricted sectors (see sector tag/sync bytes). for a further description of the nx26f080a and nx26f160 device information format, see the serial flash device information sector application note sfan-02. as shown in figure 6, the address for the device information sector address is at 5000h for both the nx26f080a and nx26f160. the device information sector is a ? read-only ? sector. this assures that all device specific information, such as the restricted sector list, is maintained and never written over inadvertently. for compatibility with applications that used the original nx26f080 (non a), which does not have a separate device information sector, a copy of the device information sector is also provided in the last two sectors of the nx26f080a (07ffh and 07feh) and nx26f160 (0fffh and 0ffeh). contact nexflash ? s serial flash applications department if you require compatibility with the nx26f080 (non a). ready/busy status after an erase/write instruction sequence has been executed, the device will become busy while it erases and writes the addressed sector ? s memory. this period of time will not exceed t wp (~5 to 30 ms based on the specified power supply operating voltage). during this time the device can be tested for a ready/busy condition via a 16-bit status value obtained in the read instruction sequence. the busy status condition (6666h) indicates that the device has not yet completed its write operation and will not accept read or write instructions. the ready status condition (9999h) indicates that the device is available for further read or write operations. note that a delay time of t rp (~30 s to 100 s depending on the voltage version being used) is required after the first low to high clock transition of the ready/busy status read. sector tag/sync bytes the first byte of each sector is pre-programmed during manufacturing with a tag/sync value of ? c9h ? . although the first byte of each sector can be changed, it is recommended that tag/sync value be maintained and incorporated as part of the application ? s sector formatting. the tag/sync values serve two purposes. first, they provide a sync-detect that can help verify if the instruction sequence was clocked into the device properly. secondly, they serve as a tag to identify a fully functional (valid) sector. this is especially important if ? restricted sector ? devices are used. restricted sector devices provide a more cost effective alternative to nx26f080a or nx26f160 devices with 100% valid sectors. restricted sector devices have a limited number of sectors (64 maximum. for the nx26f080a and nx26f160) that do not meet manufacturing programming criteria over the specified operating range. when such a sector is detected, the first byte is tagged with a pattern other than ? c9h ? . in addition to individual sector tagging, all restricted sectors for a given device are listed in the ? device information format ? (see device initialization). high data integrity applications data storage applications that use flash memory or other non-volatile media must take into consideration the possibil- ity of noise or other adverse system conditions that may affect data integrity. for those applications that require higher levels of data integrity it is a recommended practice to use error correcting code (ecc) techniques. the nexflash serial flash development kit provides a software routine for a 32-bit ecc that can detect up to two bit errors and correct one. the ecc not only minimizes problems caused by system noise but can also extend flash memory endurance. for those systems without the processing power to handle ecc algorithms, a simple ? verification after write ? is recom- mended. the nexflash serial flash development kit software includes a simple write/verify routine that will compare data written to a given sector and rewrite the sector if the compare is not correct.
1 2 3 4 5 6 7 8 9 10 11 12 nexflash technologies, inc. 5 preliminary nxsf006e-0801 08/22/01 ? nx26f080a nx26f160 c3-c0 sa11-0 da3-0 sa15-12 r31-r0 s15-s0 d0 - - - d4287 initial clock to wake device from standby (data is "don't care") command type 1h = read main sector address 000h-7ffh for nx26f080a 000h-fffh for nx26f160 device address a0-a3 pins = 0h-fh auxilary sector address 0h = to address main sector address 0-fff 5h = device information sector reserved use 00 00 00 00h for nx26f080a and nx26f160 input status bytes 9999h = ready, 6666h = busy note: delay is required during status byte read, see t rp in ac characteristics input sector data bits (536 bytes) command address reserved status data figure 5. sector read instruction - sequence and bit instruction
nx26f080a nx26f160 6 nexflash technologies, inc. preliminary nxsf006e-0801 08/22/01 ? initial clock to wake device from standby (data is "don't care") command type 2h = write main sector address 000h-7ffh for nx26f080a 000h-fffh for nx26f160 device address a0-a3 pins = 0h-fh auxilary sector address 0h = main sector address 0-fff reserved use 00 00 00 00h for nx26f080a and nx26f160 sector data bits 0-4287 (536 bytes) 16 extra clocks (data is "don't care") c3-c0 sa11-0 da3-0 a15-12 r31-r0 d0 - - - d4287 x15-x0 control data reserved address command figure 6. sector erase/write instruction - sequence and bit format
1 2 3 4 5 6 7 8 9 10 11 12 nexflash technologies, inc. 7 preliminary nxsf006e-0801 08/22/01 ? nx26f080a nx26f160 output remaining 535 bytes (4280 bits) of sector data output (rewrite )1st byte of sector with c9h tag/sync bite output two bytes of zeros (00 00h) for the is26f160 assert clk low for t reset to invoke erase/write operation and then standby operation output one clock to wake device from stand-by call read sector routine to check ready/busy and tag start sector erase/write routine return (1) yes no* device ready and sector tag valid *set flag and process accordingly upon return output command sequence: -read command c3-c0 (0002b) -main sector address sa11-0 (000-fffh) -device address da3-da0 (per state of a3, a2, a1, a0 pins) -auxilary address a15-a12 0h for main array -four reserved bytes r31-r0 (00 00 00 00h) figure 8. sector erase/write operation flow chart input first byte of data (tag/sync) from sector *set flag and process accordingly upon return return yes no* no* yes* ready? (99 99h) input remaining 535 bytes of sector data (4280 bits) return to write routine? assert clk low for t reset to reset device and invoke standby valid sector? (c9h) no start sector read routine output clock (low to high) to wake device from standby input ready/busy status s15-s0. note t rp delay time is required during status read (see ac timing and figure 10) output command sequence: -read command c3-c0 (0001b) -main sector address sa11-0 (000-fffh) -device address da3-da0 (per state of a3, a2, a1, a0 pins) -auxilary address a15-a12 0h for main array 5h device information sector -four reserved bytes r31-r0 (00 00 00 00h) yes figure 7. sector read operation flow chart note: 1. to ensure higher data integrity verify each sector write with a sector read. see high data integrity applications on page 4.
nx26f080a nx26f160 8 nexflash technologies, inc. preliminary nxsf006e-0801 08/22/01 ? device leaves standby mode at this edge read command 12-bit sector address float sio so data direction can change from device input to output status word (s15-s0): ready: 9999h or busy:6666h device releases sio line device drives sio line t reset 8 clocks 4280 clocks device address aux. address bytes 0 to 534 bytes 0 to 535 four reserved bytes (use 00 00 00 00h) 0 0 0 1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 da3 da2 da1 da0 a15 a14 a13 a12 sck sio sck sio sck sio sck sio t rp 10011001 1 0011001 msb lsb figure 9. read instruction sequence clocking
1 2 3 4 5 6 7 8 9 10 11 12 nexflash technologies, inc. 9 preliminary nxsf006e-0801 08/22/01 ? nx26f080a nx26f160 device leaves standby mode at this edge device enters standby mode after t wp write command 12-bit sector address device address 0h four reserved bytes (use 00 00 00 00h) msb lsb byte 1 byte 0 bytes 2 to 533 8 clocks 4256 clocks 8 clocks 8 clocks 16 extra clocks 8 clocks byte 535 byte 534 t reset don't care t wp sck sio sck sio sck sio sck sio 0010 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 da3 da2 da1 da0 0000 figure 10. erase/write instruction sequence clocking
nx26f080a nx26f160 10 nexflash technologies, inc. preliminary nxsf006e-0801 08/22/01 ? absolute maximum ratings (1) symbol parameter conditions range unit vcc supply voltage 0 to 7.0 v v in , v out voltage applied to any pin relative to ground ? 0.5 to vcc + 0.6 v t stg storage temperature ? 65 to +150 c t lead lead temperature soldering, ten seconds +300 c note: 1. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure beyond absolute maximum ratings (listed above) may cause permanent damage operating ranges symbol parameter conditions min max unit vcc supply voltage 26f080a-5t-r 26m080a-5t-r 4.5 5.5 v 26f080a-3t-r 26m080a-3t-r 2.7 3.6 v 26f160-5t-r 26m160-5t-r 4.5 5.5 v 26f160-3t-rs1 26m160-3t-r 3.0 3.6 v 26f160-3t-r 2.85 3.6 v t a ambient temperature, commercial 0 +70 c operating extended (1) ? 15 +80 c industrial (1) ? 40 +85 c note: 1. contact nexflash for availability of extended or industrial grade devices. dc electrical characteristics symbol parameter conditions min typ max unit v il input low voltage ? 0.4 ? vcc x 0.2 v v ih input high voltage vcc x 0.6 ? vcc + 0.5 v v ol output low voltage i ol = 2 ma, v cc = 4.5v ?? 0.45 v v oh output high voltage i oh = ? 400 a, v cc = 4.5v 2.4 ?? v v olc output low voltage cmos (1) v cc = min, i ol = 10 a ?? 0.15 v v ohc output high voltage cmos (1) v cc = min, i oh = ? 10 av cc ? 0.3 ?? v i li input leakage 0 < v in < vcc ? 10 ? +10 a i ol i/o leakage 0 < v in < vcc, output disabled ? 10 ? +10 a i cc (active) active power supply current (2) f clk 8 mhz (1/t cp ) v cc = 4.5v to 5.5v ? 15 30 ma v cc = 2.7v to 3.6v (nx26f080a) ? 510 v cc = 2.85v to 3.6v (nx26f160) ? 10 20 i ccsb (standby) standby power supply current sio = 0v or v cc , ? <1 10 a sck = 0v c in input capacitance (1) t a = 25 c, v cc = 5v or 3v ?? 10 pf frequency = 1 mhz c out output capacitance (1) t a = 25 c, v cc = 5v or 3v ?? 10 pf frequency = 1 mhz notes: 1. tested on a sample basis or specified via design or characterization data. 2. the device leaves ? standby ? power consumption after the clock transitions from low-to-high. full ? active ? power consumption starts after the correct device address has been decoded during a sector read or write sequence.
1 2 3 4 5 6 7 8 9 10 11 12 nexflash technologies, inc. 11 preliminary nxsf006e-0801 08/22/01 ? nx26f080a nx26f160 ac electrical characteristics 5v (16 mhz) 3v (8 mhz) symbol description min typ max min typ max unit t cp sck serial clock period 62 ?? 125 ?? ns t cl , t ch sck serial clock high or low time 26 ?? 57 ?? ns t cr sck serial clock rise time (1) ?? 7 ?? 5ns t cf sck serial clock fall time (1) ?? 7 ?? 5ns t ds sio setup time to sck rising edge 40 ?? 100 ?? ns t dh sio hold time from sck rising edge 0 ?? 0 ?? ns t dv sio valid after sck (2) ?? 60 ?? 115 ns t reset sck low duration for 1 ? 52 ? 10 s valid reset or standby (see figures 9 & 10) t rp read pre-data delay (see figure 9) 30 ?? 100 ?? s t wp erase/write program time (3) nx26f080a ? 35 ? 510 ms (see figure 10) nx26f160 ? 4 5.5 ? 25 32 notes: 1. test points are 10% and 90% points for rise/fall times. all other timings are measured at the 50% point. 2. with 50 pf (8 mhz) or 30 pf (16 mhz) load sio to gnd. 3. the nx26f080a and nx26f160 are designed for erase/write endurances of 10k cycles. endurance in the range of 100k cycles can be obtained using ecc software methods like those provided in the sfk serial flash development kit. sck sio read write t cp t ch t cl t ds t dh t cf t cr t dv t dv clock and data timing
nx26f080a nx26f160 12 nexflash technologies, inc. preliminary nxsf006e-0801 08/22/01 ? package information plastic tsop - 24/28-pins package code: t (type ii) notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t ? type ii) millimeters inches symbol min max min max ref. std. no. leads 24/28 a 1.00 1.20 0.039 0.047 a1 0.05 0.20 0.002 0.008 b 0.36 0.51 0.014 0.020 c 0.10 0.20 0.004 0.008 d 18.31 18.52 0.721 0.729 e 10.06 10.26 0.396 0.404 h 11.74 11.94 0.462 0.047 e 1.27 bsc 0.050 bsc l 0.43 0.584 0.017 0.023 0 5 0 5 d seating plane b e c 1 n/2 n/2+1 n e h a1 a l
1 2 3 4 5 6 7 8 9 10 11 12 nexflash technologies, inc. 13 preliminary nxsf006e-0801 08/22/01 ? nx26f080a nx26f160 ordering information size order part no. package/description (2) 8m-bit nx26f080a-3t-r (1) nxs, 28-pin, tsop (type ii) 64 rs, 3v low voltage 8m-bit nx26f080a-5t-r (1) nxs, 28-pin, tsop (type ii) 64 rs, 5v standard voltage 16m-bit nx26f 160-3t-r nxs, 28-pin, tsop (type ii) 64 rs, 2.85v-3.6v low voltage 16m-bit nx26f160-3t-rs1 nxs 28-pin, tsop (type ii) 64 rs 3.0v-3.6v low voltage 16m-bit nx26f160-5t-r (1) nxs, 28-pin, tsop (type ii) 64 rs, 5v standard voltage notes: 1. add e (extended) or i (industrial) after package designator (t) for alternative temperature grades. 2. see 26mxxx data sheet for serial flash module package. preliminary designation the ? preliminary ? designation on an nexflash data sheet indicates that the product is not fully characterized. the specifications are subject to change and are not guaran- teed. nexflash or an authorized sales representative should be consulted for current information before using this product. important notice nexflash reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. nexflash assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, nexflash shall not be liable for any damages arising as a result of any error or omission. life support policy nexflash does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure in the life support system or to significantly affect its safety or effectiveness. products are not autho- rized for use in such applications unless nexflash receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of nexflash is adequately protected under the circumstances. trademarks: nexflash tm is a trademark of nexflash technologies, inc . all other marks are the property of their respective owners.
nx26f080a nx26f160 14 nexflash technologies, inc. preliminary nxsf006e-0801 08/22/01 ?

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